Setup and speed of circuit

Thanks to my friend HL, I'm able to get this explanation into writing :):

KKCheong says:
the d'' is the data at the second register
KKCheong says:
clk' is the clock at the second register
KKCheong says:
You need to capture the data A at the second clock
KKCheong says:
for register to register, first register use the first clock. second register use the second clock
KKCheong says:
And u can see, setup time is how long the data is stable before the clock active
KKCheong says:
in this case, the real setup time is actually
KKCheong says:
--->


KKCheong says:
so, real setup time = clock period - 6.5ns
KKCheong says:
if you barely fail setup time, means, setup time = 0
KKCheong says:
real setup time = 0 = clock period - 6.5ns
KKCheong says:
clock period = 6.5ns when setup fail
KKCheong says:
to make it pass setup time, real setup > 0
KKCheong says:
clock period - 6.5ns > 0
KKCheong says:
clock period > 6.5ns